1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, particularly, the reduction of the antenna effect in an SOI device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits), and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein for many types of complex circuitry metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, complementary MOS (CMOS) technology, millions of n-channel transistors and p-channel transistors are formed on a substrate including a crystalline semiconductor layer.
A field effect transistor, irrespective of whether an n-channel transistor or a p-channel transistor is considered, typically comprises so-called pn-junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers, and—for a given extension of the channel region in the transistor width direction—on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits. As the channel length is reduced the thickness of the gate dielectric is also reduced. The scaling of the gate dielectric is limited by several factors such as defects, power supply voltage, time-dependent dielectric breakdown and leakage currents.
However plasma induced damages of gate dielectrics, called antenna effects, occurring during the overall processing of the semiconductor devices pose severe problems and may significantly affect yield and reliability of the semiconductor devices. The damages comprise plasma charging damages that particularly occur when electrical charges are collected from the plasma by the gate electrode and flow through the gate dielectric. For example, the antenna effect is caused by polysilicon, metal or contact etching and ion implantation.
An example of the antenna effect is illustrated in FIG. 1 FIG. 1 shows an SOI configuration comprising a semiconductor bulk substrate 1, a buried insulating layer 2 formed on the semiconductor bulk substrate 1 and a lightly doped or un-doped semiconductor region called channel 3 surrounded by heavily doped source and drain regions 4. A gate dielectric 5 is formed on the channel 3 and a gate electrode layer 6 of an FET device is formed on the gate dielectric 5. An interlayer dielectric 7 is formed over the structure of the FET and a contact 8 is formed in the interlayer dielectric 7 to electrically contact the gate electrode layer 6. The contact 8 is connected to a metal layer 9, for example, a first metal interconnect layer. This (floating) metal layer 9 acts as an antenna during plasma etching, for example, reactive ion etching, of the same. In fact, charges of the plasma etchant are collected by the metal layer 9 and, thus, by the gate electrode layer 6 electrically connected to the metal layer 9 via contact 8.
In order to reduce antenna effects so-called antenna rules are provided. The antenna rules may give an allowable ratio of metal area to gate area for each interconnect layer. In practical applications, violations of the rules cannot be avoided and, thus, means for fixing or accounting for such violations on the actual design have to be provided. Those means typically include the provision of protection diodes. A protection diode may be formed with an n+ implant in a p-substrate or a p+ implant in an n-well away from the source/drain regions of a MOSFET. By connecting the diode to a metal element near the gate the diode can protect the gate dielectric against charging damages.
However, antenna rules introduced for bulk technologies are conventionally not used for silicon-on-insulator (SOI) technologies. In particular, no substrate diode protection can be provided in the context of the SOI technologies. For example, a fully depleted SOI (FDSOI) cell design with wells formed below p-channel FETs and n-channel FETs does not allow for the provision of substrate diodes for fixing antenna effects.
The present disclosure provides means for reducing antenna effects in the context of SOI, in particular, FDSOI, technologies which may help to substantially overcome or at least reduce some or all of the above-mentioned issues.